1. Field of the Invention
The present invention relates to liquid crystal displays, and more particularly to line-on-glass (LOG) type liquid crystal displays that are capable of preventing deterioration in picture quality caused by a line resistance of LOG gate low voltage lines arranged on a liquid crystal display panel.
2. Description of the Related Art
Generally, liquid crystal displays (LCDs) use electric fields to control light transmittance characteristics of a layer of liquid crystal material. Accordingly, LCDs typically include a liquid crystal display panel having a plurality of liquid crystal cells arranged in a matrix pattern and a driver circuit for driving the plurality of liquid crystal cells to display a picture on the liquid crystal display panel.
The plurality of liquid crystal cells are arranged on the liquid crystal display panel at locations where gate lines cross data lines. Electric fields may be applied to the layer of liquid crystal material via pixel and common electrodes arranged on the liquid crystal display panel. Each pixel electrode is connected to a data line via source and drain electrodes of switching devices such as thin film transistors. Gate electrodes of each thin film transistor are connected to corresponding gate lines and allow pixel voltage signals to be selectively applied to corresponding pixel electrodes.
The driver circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for controlling the gate and data drivers, and a power supply for supplying driving voltages used in driving the LCD. The timing controller controls the gate and data drivers by controlling a driving timing of the gate and data drivers and by applying pixel data signals to the data driver. Driving voltages generated by the power supply include common (Vcom), gate high (Vgh), gate low (Vgl) voltages, etc. The gate driver sequentially applies scanning signals to the gate lines to sequentially drive the liquid crystal cells within the liquid crystal display panel one gate line at a time. The data driver applies data voltage signals to each of the data lines whenever a gate line is in receipt of a gate signal. Accordingly, LCDs control light transmittance characteristics of liquid crystal material using electric fields applied between pixel and common electrodes in accordance with pixel voltage signals specific to a liquid crystal cell.
Data and gate drivers are directly connected to the liquid crystal display panel and are provided as a plurality of integrated circuits (ICs). Each of the gate driver ICs and data driver ICs are mounted to the liquid crystal display panel using tape carrier package (TCP) or chip on glass (COG) techniques. Further TCP-type gate and data driver ICs are connected to the liquid crystal display panel via a tape automated bonding (TAB) technique.
TCP-type gate and data driver ICs, connected to the liquid crystal display panel by the TAB technique, receive control signals and direct current (DC) voltage signals transmitted over signal lines provided on a printed circuit board (PCB). For example, each of the data driver ICs are connected to each other in series via signal lines mounted on a data PCB, receive control signals from the timing controller, and receive pixel data signals and driving voltages from the power supply. Gate driver ICs are connected to each other in series, via signal lines mounted on a gate PCB, receive control signals from the timing controller, and receive driving voltages from the power supply.
COG-type gate and data driver ICs are connected to each other via signal lines formed using a line-on-glass (LOG) technique. Mounted on a lower glass substrate of the liquid crystal display panel, the signal lines formed using the LOG technique receive control signals from the timing controller and power supply and driving voltages from the power supply.
Even when the various driver ICs are connected to liquid crystal display panels via the TAB technique, the LOG technique is typically adopted to eliminate the PCB and provide a thinner overall liquid crystal display. For example, signal lines connecting the gate driver ICs are relatively small and are provided directly on the liquid crystal display panel. Accordingly, gate driver ICs are connected to the liquid crystal display via the TAB technique, are connected to each other in series via signal lines mounted on a lower glass substrate of the liquid crystal display panel, and receive control and driving voltage signals (i.e., gate driving signals).
Referring to FIG. 1, liquid crystal displays including LOG signal lines (e.g., formed without the gate PCB) typically include a liquid crystal display panel 1, a plurality of data TCPs 8 connected between a first side of the liquid crystal display panel 1 and a data PCB 12, a plurality of gate TCPs connected to a second side of the liquid crystal display panel 1, data driver ICs 10 mounted on the data TCPs 8, and gate driver ICs 16 mounted on the gate TCPs 14.
The liquid crystal display panel 1 includes a lower substrate 2 supporting signal lines and a thin film transistor array, an upper substrate 4 supporting a color filter array, and a layer of liquid crystal material between the lower and upper substrates 2 and 4, respectively. The liquid crystal display panel 1 further includes a picture display area 21 having liquid crystal cells arranged where gate lines 20 and data lines 18 cross each other. The data driver ICs 10 convert digital pixel data signals into analog pixel voltage signals and apply the analog pixel voltage signals to the data lines 18.
Data pads and gate pads (not shown) are arranged at respective ends of the data and gate lines 18 and 20 at an outer portion of the lower substrate 2, outside the picture display area 21. An LOG signal line group 26 is positioned within the outer area and transmits gate driving signals to the gate driver ICs 16.
Data TCPs 8 include input pads 24 and output pads 25 for electrically connecting the data driver IC 10 mounted thereon to the data PCB 12 and the data lines 18. The input pads 24 of the data TCP 8 are electrically connected to the output pads of the data PCB 12 while the output pads 25 of the data TCP 8 are electrically connected to the data pads arranged on the lower substrate 2. A first data TCP 8 is further provided with a gate driving signal transmission group 22. The gate driving signal transmission group 22 electrically connects the LOG signal line group 26 to the timing controller and power supply via the data PCB 12.
Each of the gate TCPs 14 includes a gate driving signal transmission line group 28 and output pads 30 electrically connecting the gate driver ICs 16 mounted thereon to the LOG signal line group 26 and the gate lines 20, respectively. Accordingly, the output pads 30 are electrically connected to the gate pads arranged on the lower substrate 2.
Each gate driver IC 16 sequentially applies a scanning signal (e.g., a gate high voltage signal (Vgh)) to each of the gate lines 20 in response to inputted control signals. Further, the gate driver ICs 16 apply a gate low voltage signal (Vgl) to each of the gate lines 20 not in receipt of the gate high voltage signal (Vgh).
The LOG signal line group 26 typically consists of signal transmission lines and transmits direct current (DC) voltage signals (e.g., gate high voltage (Vgh), gate low voltage (Vgl), common voltage (Vcom), ground voltage (GND), supply voltage (Vcc) signals, etc.) and gate control signals (e.g., gate start pulse (GSP), gate shift clock (GSC), gate enable (GOE) signals, etc.).
Individual signal transmission lines within the LOG signal line group 26 are arranged in a fine parallel pattern and are provided within a narrow space, similar to a space where signal lines in gate and data pads are positioned at outer portions of the picture display area 21. Signal transmission lines within the LOG signal line group 26 are formed of same metal as the gate metal layer and are arranged on the lower substrate 2. Being formed from the same material as the gate metal (e.g., AlNd, etc.), signal transmission lines within the LOG signal line group 26 typically have a resistivity of 0.046 and are formed simultaneously with the gate lines 20. Thus, the LOG signal line group 26 has a larger resistance than signal lines, typically made of a material such as copper, formed in the gate PCB. As resistance values of signal transmission lines within the LOG signal line group 26 are proportional to their lengths, the resistance of signal transmission lines increases as the distance from the data PCB 12 increases. Accordingly, gate driving signals, transmitted via the LOG signal line group 26, become attenuated, their voltage values become distorted, and the quality of pictures capable of being displayed on the liquid crystal display becomes deteriorated.
For example, distortion of the gate low voltage signal (Vgl) transmitted through the LOG signal line group 26 affects the picture quality displayed within the picture display area 21. Gate low voltage signals (Vgl) maintain the pixel voltage charged within the liquid crystal cell between intervals when the gate high voltage (Vgh) is charged within the pixel. Accordingly, as the gate low voltage signal is distorted, the pixel voltage within the liquid crystal cell also becomes distorted.
LOG gate low voltage transmission lines, arranged within the LOG signal line group 26, supply the gate low voltage (Vgl) and include a plurality of LOG gate low voltage transmission lines. The plurality of gate low voltage transmission lines electrically connect the first data TCP 8 and the plurality of gate TCPs 14, respectively. The plurality of gate low voltage transmission lines have intrinsic line resistance values proportional to their lengths, and are connected to each other in series via the plurality of gate TCPs 14. Thus, the brightness to which images may be expressed by liquid crystal cells connected to gate lines across the liquid crystal display panel becomes non-uniform. The non-uniform brightness across the liquid crystal display panel induces a cross-line phenomenon (32) that divides the screen in brightness values and thereby deteriorates the picture quality of the liquid crystal display.
Referring to FIG. 2, the gate low voltage signal (Vgl) is applied to the entire liquid crystal display panel via a relatively long transmission path and a load at a gate low voltage output terminal of the data TCP 8 is proportionally increased.
Referring to FIG. 2, a gate low voltage signal (Vgl) transmission path formed on the lower substrate 2 may equivalently be expressed as consisting essentially of an A-B transmission path and an A-C transmission path. A gate low voltage signal (Vgl) is applied to a dummy gate line GL0 on the A-B transmission path. Accordingly, the A-B transmission path typically includes a first gate low voltage line VGLL and a second gate low voltage line SDL arranged between the dummy gate line GL0 and the first gate low voltage line VGLL.
The first gate low voltage line VGLL may extend from the data TCP 8 to the lower end of the lower substrate 2 via the gate TCP (not shown). The second gate low voltage line SDL may extend from the first gate low voltage line VGLL at the lower end of the lower substrate 2 to the dummy gate line GL0 at the upper end of the lower substrate 2. The second gate low voltage line SDL crosses portions of the gate lines (not shown) arranged within a non-display area, outside the picture display area 21. Accordingly, the second gate low voltage line SDL may be formed from a source/drain metal layer and be insulated from the gate lines via a gate insulating film.
The first gate low voltage line VGLL has an intrinsic line resistance, Ra+Rb, which is determined by adding a first intrinsic line resistance, Ra, specific to the portion of the first gate low voltage line VGLL arranged between the data TCP 8 and a first gate TCP, and a second intrinsic line resistance, Rb, specific to the portion of the first gate low voltage line VGLL arranged between the gate TCPs. Similarly, the dummy gate line GL0 has a third intrinsic line resistance, Rc, and the second gate low voltage transmission line SDL has a fourth intrinsic line resistance, Rd. Thus, the total line resistance of the A-B transmission path is equal to the sum of the first to fourth line resistances, Ra+Rb+Rc+Rd.
The A-C transmission path supplies a gate low voltage signal (Vgl) to the nth gate line GLn via a corresponding gate driver IC (not shown). Accordingly, the A-C transmission path typically includes the first gate low voltage transmission line VGLL and the nth gate line GLn. The intrinsic line resistance of the nth gate line GLn is substantially equal to the third intrinsic line resistance, Rc, of the dummy gate line GL0. Thus, the total line resistance of the A-C transmission path is equal to the sum of the first to third line resistances, Ra+Rb+Rc.
The load present at the output terminal of the data TCP 8 is proportional to the total line resistance of the gate low voltage line at the output terminal of the data TCP 8. Accordingly, the total line resistance of the gate low voltage line at the output terminal of the data TCP 8 may be expressed as Ra+Rb+((Rc+Rd)/Rc). For example, assuming that Ra=15Ω, Rb=45Ω, Rc=3 kΩ and Rd=5 kΩ, the total line resistance of the A-B transmission path is 15Ω+45Ω+3 kΩ+5 kΩ=8.06 kΩ, the total line resistance of the A-C transmission path is 15Ω+45Ω+3 kΩ=3.06 kΩ, and the total line resistance of the first gate low voltage transmission line VGLL becomes 15Ω+45Ω+((3 kΩ+5 kΩ)/3 kΩ)≈3.24 kΩ.
In order to overcome the relatively large line resistance of the A-B transmission path, a relatively large load is provided at the gate low voltage output terminal of the data TCP 8. Such a large load further distorts the gate low voltage signals (Vgl) applied from the gate low voltage output terminal. Accordingly, unstable gate low voltage signals (Vgl) are applied to the gate lines within the picture display area 21 and further induce a deterioration in the picture quality. Further, differences in gate low voltage signals for each gate driver IC are enlarged due to the line resistance within of the gate low voltage line. Accordingly, the aforementioned cross-line phenomenon is magnified across the liquid crystal display.
The first gate low voltage line VGLL is typically positioned at the outermost portion of the lower substrate 2, is formed relatively shorter in length than other LOG signal lines, and is patterned to have a maximized line width within a confined space. As the first gate low voltage line VGLL is positioned at the outermost portion of the lower substrate 2, a gate low voltage signal (Vgl) applied to the dummy gate line GL0 passes the first gate low voltage line VGLL and the second gate low voltage line SDL. Since the A-B transmission path (VGLL+SDL) of the gate low voltage signal (Vgl) applied to the dummy gate line GL0 is longer than the A-C transmission path of the gate low voltage signal (Vgl) applied to another gate line (eg., GLn), the intrinsic line resistance of the A-B transmission path is larger than intrinsic line resistance of the A-C transmission path. Accordingly, a voltage associated with a gate low voltage signal (Vgl) applied to the dummy gate line GL0 is reduced compared to a voltage associated with the gate low voltage signal (Vgl) applied another gate line (e.g., GLn). Accordingly, capacitance values of storage capacitors Cst connected to the dummy gate line GL0 are reduced compared to capacitance values of storage capacitors Cst connected to another gate line (e.g., GLn) such that liquid crystal cells connected to the dummy gate line GL0 express images at a greater brightness than liquid crystal cells connected to another gate line (e.g., GLn).